Design Engineer

RTL Design Engineer

Experience : 3 years

Location : Bangalore

Familar with RTL design and Power flow.

SoC Interconnect for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. This position includes but no limited to:-

Familar with Power flow for RTL design.

NoC design lead part of BDC infrastructure (NoC/Interconnect) core team

Responsible for specification, design and implementation of interconnect and related IPs

Actively work with SoC team, verification team, physical design team, Soc Floorplan, core teams and various other interconnect teams in various other sites

Partner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptions

Minimum Qualifications:

5+ years of solid experience in SoC design

Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite/NoC concepts

Good knowledge of Digital Design and RTL development

Hands-on experience with SoC Design, Verilog RTL coding

Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug

Working knowledge of Lint, CDC, PLDRC, CLP etc

Manage SoC dependencies, planning and tracking of all front-end design related tasks

Interested,please share your updated resume to janagaradha.n@acldigital.com