Circuit and Library Characterization: Standard Cell and SRAM

About Company

At 7Rays Semiconductors (https://7rayssemi.com/), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Role: Circuit and Library Characterization: Standard Cell and SRAM

Location: Bangalore, India

Experience: 10+ Years or higher

Job Description

Strong expertise in characterization and modeling of standard cell libraries and SRAM macros across multiple PVT corners, ensuring accurate timing, power, and noise modeling for advanced technology nodes.

Deep understanding of SRAM architectures including single-port, dual-port, two-port, pseudo dual-port, and multiport register file implementations, with the ability to interpret transistor-level designs and ensure accurate characterization coverage.

Experience in characterizing SRAM sub-systems and peripheral circuits, including control logic, I/O latches, clock gating, row decoders, read/write assist circuits, sense amplifiers, clocking networks, tracking circuits, precharge/discharge paths, reset logic, and internal timing margins.

Proficient in SRAM macro characterization and validation, including modeling of:

• Read/write timing arcs
• Bit/byte write functionality
• Assist and margin control circuits
• Address programmability
• Redundancy and repair mechanisms
• DFT features and test modes
• Power gating behavior

Strong experience in standard cell library characterization, including sequential and combinational cells such as latches, flip-flops, clock gating cells, adders, multipliers, and custom arithmetic blocks.

Hands-on expertise in generating and validating complete timing, power, and noise models, including:

• NLDM/CCS timing and power models
• LVF (Liberty Variation Format) for statistical timing analysis
• Internal power and leakage characterization
• State-dependent and multi-mode arcs
• EM/IR aware power modeling where applicable

Proven experience performing comprehensive Liberty QA and sign-off checks, including timing consistency, arc completeness, waveform integrity, and correlation with SPICE simulations.

Strong ability to debug characterization issues, improve model accuracy, and ensure correlation between SPICE simulations, characterization outputs, and STA results.

Experience developing and maintaining automated characterization flows and regression frameworks for large libraries and complex memory macros.

EDA Tools and Flows

Hands-on experience with industry-standard characterization and simulation tools including:

Circuit Simulation & Extraction

• Cadence Virtuoso
• StarRC, Quantus
• HSPICE, PrimeSim XA, Spectre, PrimeSim CCK

Variation, Modeling & Analysis

• Solido HSV
• Spectre FMC
• NanoTime

Library Characterization

• Liberate
• Liberate MX
• SiliconSmart

Experience in large-scale characterization automation, regression management, and library QA flows for standard cell and memory IP delivery.