ASIC RTL Designers Lint/CDC

Role: RTL Design Integration Quality Checks

No of Positions: 8

Experience : 5-6 Years

Joining Time: immediate to 1 Month

Location : Bangalore

JD:

5 -6 years of experience in ASIC front end design and quality check

Strong fundamental knowledge of digital design, Verilog and scripting language

Working knowledge for FE flows like Lint, CDC, synthesis, and other quality checks.

Experience in multiple clock and voltage domain design is preferred

Understanding of UPF and experience in low power checks is preferred.

Responsibilities:

RTL Front-end quality checks Lint, CDC, synthesis, low power checks.

RTL Quality Checks and Sign-Offs ( Subsystem & SoC Level) Lint, CDC, RDC, FC / DC Synthesis, MBIST Insertion, Logic Equivalence checks, Low Power Static Checks (VCLP)

Write and debug constraints for above QA flows.

Work with subsystem and/or SOC integration team on design integration and debugs.