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ASIC RTL Design Lead/Engineers

eInfochips (An Arrow Company)

5 - 10 years

Bengaluru

Posted: 28/02/2026

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Job Description

Were Hiring Digital Design Engineers | Bangalore

We are opening new positions for Senior and Junior Digital Design roles!

Senior Digital Design Engineer (10+ yrs)

Digital architecture, RTL, lowpower, synthesis & timing

Strong in RTL, CDC, STA, PnR, UPF, SystemVerilog

Junior Digital Design Engineer (3+ yrs)

Implement digital blocks

RTL flow: Lint / CDC / CLP

Scripting: Perl / TCL / Python

Interested or know someone who fits? Feel free to share profiles!

sivajyothi.kunche@einfochips.com

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