ASIC RTL Design Engineers

Hi Folks,

We are looking for an experienced Senior ASIC RTL Design Engineer to join our growing semiconductor design team.

Location: Bangalore

Experience: 5-12 Years

Notice period: Immediate

Job Description:

Microarchitecture, Module design and simulation

Digital design, implementation and integration RTL Coding, Lint, CDC, and Synthesis.

Develop design constraints and coordinate to debug both functional and DFT test issues.

Synthesis and P&R constraint generation, including clock tree specification

Scan insertion and pattern generation

Support IP/Design Verification/Firmware/Software System to provide the necessary support for timely closure of assigned blocks design and implementation issues.

Digital design knowledge

System knowledge

Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation, Lint, CDC/RDC and power intent checks UPF.

Familiarity with Cadence, Synopsis design tools

Send your resume to: pujasaha@mirafra.com

Be part of a team where technology meets innovation lets design the future together!