ASIC Design Verification Engineer (SoC/Subsystem)

Position: Senior/Principal ASIC Design Verification Engineer (SoC/Subsystem)

Location: Bangalore

Experience: 8+ Years

Hiring Principal Design Verification Engineer with strong SoC/Sub-system level UVM experience for our opportunities in Bangalore and Hyderabad. If youre passionate about tackling complex verification challenges, apply now to explore this role further.

Job Description:

• 8+ years of hands-on ASIC verification experience with strong expertise in SystemVerilog, UVM, SVA.
• Own verification of complex SoC/subsystems including planning, UVM environment development, test creation, and coverage closure.
• Strong experience debugging complex issues, analyzing waveforms/logs, and driving functional/code/assertion coverage to closure.
• Work closely with RTL, DFT, Architecture teams and support silicon bring-up and post-silicon correlation.
• Experience with standard interfaces (AXI/ACE, DDR, PCIe), coherency, low-power modes, resets, and system-level validation.