Analog Layout engineer

Mandatory Skills:

• 210 years of hands-on Analog Layout experience
• Strong expertise in Cadence Virtuoso
• Deep understanding of matching techniques (common-centroid, interdigitation)
• Experience with advanced nodes (FinFET preferred)
• Solid knowledge of DRC/LVS, EM/IR, antenna rules

Job Description:

• Perform full-custom analog/mixed-signal layout for high-performance IPs
• Handle layout of op-amps, LDOs, PLLs, ADC/DACs, SERDES, and memory peripherals
• Ensure layout meets matching, symmetry, noise, and reliability requirements
• Own DRC/LVS/ERC closure and layout sign-off
• Work closely with analog design, verification, and PD teams
• Optimize layout for performance, area, and yield
• Mentor junior layout engineers and review layouts

Please send resume to kalavathi.srinivas@acldigital.com