Analog Layout Design Engineer

Title: Analog Layout Design Engineer

Experience:4-7 years

Location: Hyderabad

Job Description

We are seeking an experienced Analog Layout Design Engineer to work on cutting-edge TSMC advanced technology nodes (16nm, 12nm, 7nm, 5nm, 3nm) . The role involves full-cycle custom layout of high-performance analog and mixed-signal IPs, with strong emphasis on layout quality, reliability, and silicon success.

Key Responsibilities

• Perform full-custom analog and mixed-signal layout for blocks such as:
• PLL, ADC/DAC, LDO, Bandgap, SerDes, high-speed I/O, memory peripherals
• Work extensively on TSMC lower/advanced nodes (16nm FinFET and below)
• Apply advanced matching techniques (common-centroid, inter-digitization, symmetry)
• Handle device placement, routing, shielding, and EM/IR-aware layout
• Run and debug DRC, LVS, ERC, ANT, DFM, and reliability checks
• Address FinFET-specific layout constraints (quantization, orientation, poly rules)
• Collaborate closely with analog designers, PD, and foundry teams
• Optimize layout for performance, area, yield, and manufacturability
• Support tape-out, silicon bring-up, and post-silicon debug

Required Qualifications

• Bachelors or Masters degree in Electrical / Electronics Engineering
• 5+ years of hands-on experience in analog layout design
• Strong experience in TSMC advanced nodes (16nm / 12nm / 7nm / 5nm / 3nm)
• Proficiency with Cadence Virtuoso (Layout XL/GXL)
• Deep understanding of:
• Matching, noise, parasitics, latch-up, ESD
• EM/IR, reliability, and DFM rules
• Experience with FinFET layout methodologies
• Solid knowledge of process design rules and foundry guidelines

Preferred Skills

• Experience with high-speed or precision analog blocks
• Knowledge of TSMC reliability rules and sign-off flows
• Exposure to automation / SKILL scripting
• Prior successful tape-outs in advanced nodes

Tools & Environment

• Cadence Virtuoso, Calibre (DRC/LVS), Assura/PVS
• TSMC PDKs and advanced node rule decks