Analog Layout Design Engineer

Job Title:Analog Layout Engineer Advanced / Lower Nodes (TSMC)

Experience:4 -7 Years

Location: Hyderabad (F2F)

Job Summary

We are seeking an experienced Analog Layout Engineer to design and implement high-performance analog and mixed-signal IC layouts in advanced CMOS technology nodes (e.g., 28nm, 16nm, 7nm, 5nm, 3nm) at TSMC. The role requires close collaboration with analog design, verification, and foundry teams to ensure robust, manufacturable, and high-yield layouts.

Key Responsibilities

• Design and deliver full-custom analog and mixed-signal layouts for advanced TSMC technology nodes
• Handle layout of blocks such as LDOs, PLLs, ADC/DACs, SerDes, amplifiers, bandgaps, clocking, and IOs
• Apply advanced layout techniques:
• Matching, symmetry, common-centroid, interdigitation
• Guard rings, shielding, substrate isolation
• EM/IR-aware routing and reliability-driven layout
• Ensure compliance with TSMC DRC/LVS/DFM rules, including advanced node-specific constraints
• Address parasitics, coupling, noise, and variability challenges in lower nodes
• Perform PEX extraction and support post-layout simulation and silicon debug
• Work closely with analog designers to optimize layout for performance, yield, and reliability
• Interact with TSMC foundry teams for rule clarifications, waivers, and silicon issues

Required Qualifications

• Bachelors or Masters degree in Electrical Engineering or related field
• 5+ years of hands-on analog layout experience (less for junior roles)
• Strong experience in TSMC advanced nodes (28nm preferred)
• Expertise with Cadence Virtuoso layout environment
• Solid understanding of device physics, matching, and layout-dependent effects (LDE)
• Proven ability to handle complex DRC and advanced node constraints

Preferred Qualifications

• Experience with FinFET nodes (16nm/7nm/5nm/3nm)
• Familiarity with EM/IR, antenna rules, and reliability analysis
• Experience in high-speed or low-noise analog designs
• Tape-out experience on multiple TSMC advanced nodes
• Knowledge of DFM, yield enhancement, and silicon correlation