Analog Design Engineer with High-speed IO design

Job Summary

Seeking an Analog Design Engineer with 510 years of experience in highspeed I/O circuit design to develop highperformance analog and mixedsignal IPs. The role involves architecture definition, circuit design, simulation, and silicon validation for advancednode highspeed interfaces.

Key Responsibilities

• Work on HighSpeed I/O and SerDes PHY design, including PLLs, CDRs, equalizers, and multiGbps analog blocks.
• Design/optimize TX/RX frontends, PLL/DLL/CDR circuits, equalization (CTLE/DFE/FFE), and bias/termination/ESD structures.
• Lead blocklevel architecture and circuit development for highspeed I/O subsystems.
• Run transistorlevel simulations (AC, transient, noise, jitter, BER).
• Handle prelayout and postlayout verification with parasitic extraction.
• Address signal integrity issues such as channel loss, crosstalk, and reflections.
• Support layout floorplanning and reviews; collaborate with digital, physical design, packaging, and system teams.
• Participate in silicon bringup, lab testing, and debug.
• Ensure spec compliance and PVT robustness; mentor junior engineers.

Required Qualifications

• Bachelors or Masters in Electrical Engineering or related field.
• 510 years of analog/mixedsignal design experience.
• Strong background in highspeed I/O design in CMOS.
• Knowledge of jitter, noise, BER, signal integrity, and channel modeling.
• Proficiency with SPICE tools (Spectre, HSPICE, Eldo).
• Strong understanding of CMOS device physics and PVT variation.
• Experience in advanced technology nodes; able to work independently with strong ownership.