AMS Verification

Key Responsibilities

• Develop AMS verification environments using SystemVerilog/UVM, Verilog-AMS, and tools like Cadence Xcelium or Incisive for mixed-signal IP/SoCs.
• Build behavioral models for analog blocks (e.g., PLLs, LDOs, SerDes) and perform real-number modeling (RNM) with validation.
• Execute test plans, regression runs, debug simulations, and analyze coverage for power management or DDR interfaces.
• Collaborate with analog/digital design teams on top-level integration and report verification progress/documentation.

Required Qualifications

• Bachelor's/Master's in Electrical Engineering, VLSI, or related field.
• 3-8 years in AMS verification, with hands-on SystemVerilog/UVM, SPICE co-simulation, and scripting (Python/Perl/TCL).
• Strong grasp of mixed-signal fundamentals, including analog/digital debug and metric-driven verification (MDV)