Job Title: Senior ASIC Verification Engineer

Location: Hyderabad, Telangana

Experience: 8+ Years

KEY RESPONSIBILITIES

Project Leadership

Help develop test plan definition

Micro-architecture design verification, RTL verification, and documentation

Top-level and block-level functional and performance verification, and system level use-case verification; and

Support test program development, chip validation, and chip life until production maturity.

Team Management and Building

Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.

Qualifications

8+ years of experience in UVM verification and UVM environment development (must have)

Proficient in test plan definition and testcase development in C/Assembly/System Verilog

Expertise in verifying design at RTL level and gate-level simulation

Good understanding of coverage analysis, performance verification and use-case verification.

Must have worked on AMBA AXI, AHB, APB protocols

Should have worked on verifying interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.

Experience in functional test vector development and post-silicon bring-up/debug.

Fluency with scripting languages (e.g., Perl, Python, Shell); and

Experience in working with repository management tools like Bitbucket/ Jenkins and bug tracking tools like JIRA.

Verification Engineer