TCS Virtual Interview_Design Verification (DV) Engineer

Design Verification (DV) Job Description

Experience Range: 3 to 15+ Years

Location: Bangalore / Hyderabad / Noida / Ahmedabad/ Chennai/ Mumbai/ Pune

Role Overview

The Design Verification (DV) Engineer is responsible for ensuring functional correctness, performance, and reliability of ASIC and SoC designs using coverage-driven verification methodologies. The role spans IP, subsystem, and full-chip verification using SystemVerilog/UVM, assertion-based verification, protocol verification, and power-aware simulation, working closely with RTL, Architecture, DFT, PD, and Silicon Validation teams.

Core Responsibilities (All Levels)

• Develop and execute verification plans aligned with design specifications
• Design and implement UVM-based verification environments and testbenches
• Create and run directed and constrained-random test cases
• Analyze simulation results, debug failures, and report root causes
• Collect and close functional, code, and assertion coverage
• Collaborate with cross-functional teams to achieve first-pass silicon success

Senior Design Verification Engineer 3 to 5 Years

• Perform IP or block-level verification using SystemVerilog and UVM
• Develop basic sequences, drivers, monitors, and scoreboards
• Execute regressions and debug functional failures
• Work on functional and code coverage collection
• Assist in assertion development and protocol checking

Lead Design Verification Engineer 6 to 9 Years

• Own IP or subsystem-level verification from plan to signoff
• Architect reusable and scalable UVM environments and components
• Drive coverage-driven and constraint-random verification strategies
• Perform power-aware verification using UPF
• Support gate-level simulations, CDC/RDC, and lint checks
• Mentor junior engineers and review verification quality

Member Technical Staff / Principal Design Verification Engineer 10+ Years

• Define verification architecture and strategy for full-chip SoCs
• Own SoC-level verification execution and coverage signoff
• Lead cross-IP, interconnect, and NoC verification
• Drive emulation, acceleration, and FPGA prototyping strategies
• Mentor DV teams and influence verification methodology improvements
• Interface with customers and stakeholders for quality and delivery

Tools & Skills

• Languages & Methodologies: SystemVerilog, UVM, SVA
• Simulators & Debug: VCS, Xcelium, Questa, Verdi
• Coverage: Functional, Code, Assertion Coverage
• Protocols: AMBA (AXI/AHB/APB), PCIe, USB, DDR, SPI, I2C, UART
• Power-Aware Verification: UPF-based simulation
• Scripting: Python / Perl / Shell (preferred)

Education

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering

Regards,

Priyankha M