SystemC / TLM Modeling Engineer

Hands-on experience in SystemC / TLM 2.0 modeling for SoC-level architectures.

Strong understanding of industry-standard protocols, with experience in one or more of the following: PCIe, CXL, Ethernet, USB, UFS.

Proficient in C/C++-based model development and SoC integration.

Solid understanding of bus interfaces and protocols such as AXI, AHB, and QSB.

Experience working in highly collaborative, cross-functional environments involving multiple stakeholders.

Good understanding of DDR design and SoC-level performance considerations.

Familiarity with SoC DV, VI, RUMI, and performance validation methodologies.

Strong academic background with a good academic score in Engineering (Bachelors or Masters in relevant discipline).