SystemC Modeling Engineer

SystemC Modeling Engineer

Location: Bengaluru

Experience: 8+ Years

Role Overview

We are seeking an experienced SystemC Modeling Engineer to develop and validate high-performance transaction-level and cycle-accurate models for complex SoCs and IPs. The role requires strong expertise in SystemC, C++, and verification methodologies, with close collaboration across Architecture, RTL, and Design Verification teams.

Key Responsibilities

• Develop and maintain SystemC/TLM-2.0 models for SoC and IP subsystems.
• Build cycle-accurate and transaction-level reference models for architectural exploration and functional validation.
• Drive Model-RTL correlation and debug functional mismatches.
• Collaborate with Architecture, RTL, and DV teams to define modeling requirements and validation strategies.
• Develop validation frameworks, test scenarios, and automated regression flows.
• Analyze performance, latency, and corner cases to ensure model accuracy.
• Enhance modeling methodologies and automate flows using Python and scripting languages.
• Support pre-silicon verification and early software enablement.

Technical Skills

• Strong expertise in SystemC, TLM-2.0, and modern C++.
• Hands-on experience in transaction-level and cycle-accurate modeling.
• Good understanding of Design Verification methodologies and Model-RTL correlation.
• Experience with SystemVerilog, UVM, and simulation/debug environments.
• Knowledge of computer architecture, memory subsystems, and interconnect protocols such as PCIe, AXI, DDR, Ethernet, or NoC.
• Proficiency in Python, Shell scripting, and Linux development environments.
• Familiarity with virtual platforms and performance modeling is desirable.

Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, Computer Science, or related disciplines.
• 8+ years of experience in Design Verification and SystemC-based modeling for complex SoCs.
• Proven track record of delivering robust models and supporting first-pass silicon success.

Mandatory Skills

• SystemC/TLM-2.0
• C++
• Design Verification (SystemVerilog/UVM) with Model-RTL Correlation