STA Engineer (Static Timing Analysis)

Job Title: STA Engineer (Static Timing Analysis)

Experience Level: 5+ years

Location: Pune, India

Job Summary:

We are looking for a skilled Static Timing Analysis (STA) Engineer to perform fullchip and blocklevel timing analysis for advanced SoC designs. The candidate will work closely with Design, PD, and Signoff teams to ensure timing closure across all modes and corners for highperformance ASICs.

Key Responsibilities:

• Perform block and fullchip STA across multiple modes and corners
• Develop and validate timing constraints (SDC) including clocks, IOs, CDC paths, and exceptions
• Analyze and resolve setup, hold, recovery, removal, and pulse width violations
• Perform timing signoff using industrystandard STA tools
• Support clock tree analysis, skew management, and onchip variation (OCV/AOCV/POCV) closure
• Identify and debug issues related to false paths, multicycle paths, and constraints quality
• Collaborate with Physical Design, RTL, and Synthesis teams for timing closure
• Review ECOs and ensure timing cleanup postECO
• Participate in chip signoff reviews and tapeout activities

Required Skills & Qualifications:

• Strong handson experience in Static Timing Analysis for ASIC/SoC designs
• Proficient with STA tools such as Synopsys PrimeTime (mandatory)
• Solid understanding of timing concepts: setup/hold, CPPR, CRPR, OCV/AOCV/POCV
• Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm optional)
• Strong skills in SDC creation and validation
• Understanding of clocking architectures (PLL, clock gating, multiclock designs)
• Experience in lowpower timing analysis (UPF/CPF preferred)
• Working knowledge of Linux environment and scripting (Tcl, Perl, Python preferred)

Good to Have

• Experience in timing signoff for highfrequency designs
• Familiarity with SI / Crosstalk timing analysis
• Exposure to DFT timing paths
• Knowledge of ECO flows and timing optimization techniques
• Experience working across multiple SoC programs