STA Engineer

Job Title: STA Engineer (5+ Years Experience)

Job Summary:

We are looking for an experienced STA Engineer to handle full-chip timing analysis and closure for advanced semiconductor designs. The candidate will be responsible for ensuring timing sign-off across all corners and modes, contributing to successful tape-out.

Key Responsibilities:

Perform full-chip Static Timing Analysis (STA) across all PVT corners and modes

Drive timing closure for setup/hold, recovery/removal, and signal integrity issues

Analyze and debug timing violations and provide effective fixes

Work closely with Physical Design, RTL, and DFT teams for timing convergence

Handle constraints development, SDC validation, and timing exceptions

Perform sign-off checks including OCV/AOCV/POCV, SI, and cross-talk analysis

Ensure timing closure for complex SoCs and support tape-out activities

Required Skills:

5+ years of experience in STA (full-chip preferred)

Strong hands-on experience with tools like PrimeTime / Tempus

Deep understanding of timing concepts, constraints, and sign-off methodologies

Experience with MMMC (Multi-Mode Multi-Corner) analysis

Knowledge of advanced nodes is a plus

Scripting skills (TCL/Python/Perl) preferred

Education:

B.Tech / M.Tech in Electronics / Electrical / VLSI or related field

Location: Bengaluru

Experience: 5+ Years