STA Engineer
LeadSoc Technologies Pvt Ltd
2 - 5 years
Bengaluru
Posted: 04/04/2026
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Job Description
Hiring: Senior STA Engineer | 5+ Years | VLSI
We are looking for an experienced STA Engineer with 5+ years of expertise in timing analysis and closure for advanced semiconductor designs.
Key Responsibilities:
- Perform Static Timing Analysis (STA) at block and full-chip level
- Drive timing closure (setup, hold, recovery, removal)
- Develop and validate SDC constraints
- Analyze multi-corner, multi-mode (MCMM) timing scenarios
- Debug complex timing violations and path issues
- Collaborate with Physical Design, RTL, and Signoff teams
- Support signoff timing and tape-out activities
Required Skills:
- Strong hands-on experience with PrimeTime (Synopsys)
- Good understanding of timing concepts, clocking, and path analysis
- Experience in MCMM timing closure
- Knowledge of signal integrity (SI) and OCV/AOCV/POCV concepts
- Familiarity with Physical Design flow (Innovus/ICC2)
- Strong scripting skills (TCL / Shell / Python)
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