Senior STA Engineer

JD For STA

Hands-on experience on Synthesis, Logical Equivalence check and Static Timing analysis.

Hands-on with the Tempus/PT to fix pre and post STA timing.

Knowledge of the Timing closure on Sub system level / Block level and Chip level.

Ability to generate the Manual ECOs to fix timing violations and DRVs.

Aware of Clock Tree Synthesis How the tool builds the Clock tree and various exceptions that can be given for better balancing of synchronous clocks

Thorough understanding of various modes that are seen in DFT ability to constrain, validate and time the DFT modes

Good understanding on constraint development.

Good Knowledge of TCL scripting and UNIX env.

Leading the team 1 to 2 team members by guiding and mentoring on the STA /Synthesis.

Should Co-ordinate with design team counterparts in RTL design, Physical design and DFT.

Good communication skills and collaborate with people and functions across sites.