Senior Physical Design Engineer

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.

Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolves design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolves Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities.

Tessolves clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.

For more details, visit www.tessolve.com.

Role Overview

We are looking for a Senior Physical Design Engineer with strong handson experience in fullchip and/or blocklevel implementation. The ideal candidate should have solid exposure to advanced nodes and be comfortable working in a fastpaced, multiclient environment.

Key Responsibilities

• Handle endtoend physical design implementation from RTL to GDSII
• Blocklevel / Fullchip Floorplanning, Power Planning, Placement, CTS, Routing
• Perform timing closure including setup, hold, and clock skew optimization
• Run and close Physical Verification (DRC/LVS)
• IR Drop and EM analysis, congestion analysis, and mitigation
• Debug and resolve timing, power, and signal integrity issues
• Work closely with RTL, STA, DFT, and Verification teams
• Support tapeout activities and customer deliverables
• Mentor junior engineers and review PD flows (for senior candidates)

Required Skills & Qualifications

• 6+ years of handson experience in Physical Design / VLSI Backend
• Strong expertise in Place & Route and Timing Closure
• Experience in advanced technology nodes (28nm and below preferred)
• Good knowledge of lowpower design techniques
• Strong understanding of clocking methodologies and constraints
• Proficiency with PD tools such as:
• Synopsys: ICC2, PrimeTime
• Cadence: Innovus, Tempus
• Scripting skills in TCL / Perl / Python (preferred)
• Ability to work independently and in teamoriented environments

Good to Have

• Fullchip ownership or tapeout experience
• Clientfacing or multiproject exposure
• Experience working in services / consulting environments
• Prior mentoring or lead responsibilities

Why Join Tessolve?

• Work with global semiconductor leaders
• Exposure to diverse projects and advanced nodes
• Strong learning curve and career growth opportunities
• Collaborative and technically strong engineering culture
• Competitive compensation and benefits

Interested candidates can share their resumes at indumathi.esakanooti@tessolve.com

or reach out at +91 80502 37819 for more details.