Senior Design Verification Engineer

IP & SoC Verification Engineers

Experience : 5-15 years

Location : Bangalore

We are looking for professionals with 515 years of experience in Verilog, SystemVerilog, UVM, Constrained Random Verification, Functional Coverage, and SoC/IP verification.

Hands-on expertise in ARM/RISC-V based SoCs, Mixed Signal Verification, Formal Verification, AMS simulations, and Gate Level Simulations will be highly valued.

If you have strong debugging, root-cause analysis, and testbench/VIP development skills with a passion for complex SoC verification, we would love to connect with you.

Share your profile to: janagaradha.n@acldigital.com

Notice Period: 030 Days