RTL Power Design Engineer

Job Summary:

The RTL Power Design Engineer will play a critical role in enhancing our system-on-chip (SoC) architectures by implementing innovative low-power solutions. You'll collaborate with cross-functional teams to ensure optimal power performance, directly impacting the efficiency and effectiveness of our product offerings.

Key Responsibilities:

• Design and implement low power architectures for SoCs, ensuring adherence to industry standards and best practices.
• Analyze and apply power-saving techniques, including Dynamic Voltage and Frequency Scaling (DVFS) and power gating.
• Perform low-power static checks using 1801 rule sets and conduct power implementation reviews.
• Conduct hands-on evaluations with low-power static checkers such as CLP and VCLP to ensure compliance and efficiency.
• Develop and refine power grids and power distribution networks (PDNs) for optimum power management integrated circuits (PMICs), including SMPS and LDO.
• Utilize power analysis, estimation, and reduction tools such as PowerArtist and Prime-Power RTL to drive power optimization.
• Leverage scripting skills in Python, Perl, or TCL to automate processes and enhance design methodologies.

Requirements:

• Minimum of 3-5 years of experience in RTL design with a strong focus on low power architecture.
• In-depth understanding of power saving techniques, including DCVS and power gating methodologies.
• Proficiency with 1801 rule set and expertise in low power static checks.
• Hands-on experience with low power static checkers (CLP/VCLP) and their implementation.
• Experience with SOC power grids and power distribution networks, demonstrating knowledge of PMIC design including SMPS and LDO.
• Familiarity with power analysis, estimation, and reduction tools like PowerArtist/Prime-Power RTL and PTPX NL.
• Strong scripting skills in languages such as Python, Perl, or TCL; expertise in automation is a significant plus.