RTL design

Hiring RTL Synthesis Engineers | Bengaluru

We are looking for skilled RTL Synthesis Engineers to join our growing semiconductor team.

Location: Bengaluru

Experience: 5+ Years

Key Requirements:

Strong experience in RTL Synthesis and Timing Closure

Hands-on experience with Synopsys Design Compiler

Good understanding of ASIC design flow

Experience with constraint development and optimization

Knowledge of STA concepts and timing analysis

Ability to debug synthesis and timing-related issues

If you're interested in exploring this opportunity, please share your updated resume