RTL Design Engineer
Mirafra Technologies
3 - 8 years
Bengaluru
Posted: 09/04/2026
Job Description
Hi Folks,
We are looking for an experienced ASIC RTL Design Engineer to join our growing semiconductor design team.
Location: Bangalore
Experience: 3-8 Years
Notice period: Immediate
Job Description:
Experience in Logic design / RTL coding.
Experience is SoC design and integration.
Experience in Verilog/System-Verilog.
Experience in Multi Clock designs, Asynchronous interface.
Experience in using the tools in ASIC development such as Lint and CDC.
Experience in Synthesis / Understanding of timing concepts is a plus.
Experience in ECO fixes and formal verification.
Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
Send your resume to: pujasaha@mirafra.com
Be part of a team where technology meets innovation lets design the future together!
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