Principal RTL Engineer – FPGA Debug & EDA Architecture

About Lattice

At Lattice, we believe in building technology with focus and intent.

We develop low-power programmable solutions that enable innovation across edge AI, connectivity, and security. Our teams work across silicon, software, and systemswith a strong emphasis on ownership, speed, and real impact.

Here, engineers dont just contribute to parts of a systemthey help define how the system works end-to-end, including the tools that bring silicon to life.

Were looking for a Principal RTL Engineer to lead the architecture and development of FPGA debug infrastructure within Lattices tool ecosystem.

This is a unique opportunity to work on on-chip debug, observability, and instrumentation capabilities, shaping how engineers analyze and optimize designs on Lattice platforms.

Youll operate at the intersection of RTL, FPGA architecture, and tooling, with the ability to influence both design and user experience.

What Youll Do

• Architect and develop FPGA debug engines and instrumentation IP
• Define scalable debug and observability frameworks for complex designs
• Translate product requirements into robust RTL architectures and specifications
• Drive RTL implementation with strong focus on performance, usability, and integration into tool flows
• Collaborate with software, UI, and validation teams to deliver cohesive debug experiences
• Influence EDA workflows and debug methodologies across the stack
• Guide silicon bring-up and ensure alignment between design and debug capabilities
• Mentor engineers and elevate design and architecture practices

What You Bring

• 12+ years of experience in RTL design and FPGA-based systems
• Strong expertise in SystemVerilog/Verilog (or VHDL)
• Deep experience in FPGA debug, bring-up, and design visibility
• Hands-on experience with simulation, synthesis, and debug tool flows
• Strong understanding of hardware-software interaction in debug environments
• Experience with complex protocols such as:
• PCIe, Ethernet, DDR, SerDes
• Proficiency in scripting/programming (Python, TCL, C/C++)
• Proven ability to drive architecture and influence system-level design

Nice to Have

• Experience contributing to debug frameworks, instrumentation, or design visibility features
• Exposure to environments focused on EDA tooling or FPGA platforms
• Strong interest in improving developer workflows and productivity

Why This Role

• Opportunity to define how FPGA designs are debugged and analyzed
• High ownership in a focused, high-impact team environment
• Work across RTL, architecture, and toolingnot just one layer
• Visibility into end-to-end silicon and tool interaction