Physical Verification Engineer

Hiring: Physical Verification Engineer

We are looking for a talented Physical Verification Engineer to join our VLSI team and contribute to high-quality chip design and signoff.

Key Responsibilities:

• Perform DRC, LVS, ERC, and Antenna checks
• Debug and resolve physical verification violations
• Work closely with Physical Design and Layout teams
• Execute block-level and full-chip verification
• Support signoff and tape-out activities
• Maintain and enhance verification flows and runsets

Required Skills:

• Hands-on experience with Calibre / ICV / Pegasus
• Familiarity with Innovus (Cadence) and PD flow understanding
• Strong knowledge of DRC, LVS, and physical verification methodologies
• Basic understanding of PEX (Parasitic Extraction)
• Experience with Unix/Linux environment
• Scripting knowledge (Shell / Python / TCL) is a plus

Qualifications:

• B.E / B.Tech / M.Tech in Electronics / Electrical / VLSI
• Relevant experience in Physical Verification (3+ years preferred)