Physical Design & STA Engineer

Company Description

AI Chips specializes in developing custom chip solutions to accelerate Machine Learning (ML) for practical, real-world applications. Our advanced ASIC and FPGA solutions are designed to meet the industry's demand for devices with lower Size, Weight, Power, and Cost (SWaP-C) compared to traditional CPU and GPU designs. AI Chips is at the forefront of innovation, providing tailored silicon solutions that meet high-performance needs while maximizing efficiency and cost-effectiveness. We are passionate about redefining possibilities in AI hardware technology.

Role Description

AI Chips is seeking a hands-on Physical Design & STA Engineer with 5-10 years of experience and a strongtrack recordof5-10tape outs to join our team in a full-time capacity. This on-site role, based inKolkata, India,joininga small team to execute physical implementation and Static Timing Analysis (STA) across various projects, with an emphasis on AI silicon. The role includesfloorplanning, timing closure, place and route (PnR), and collaborating with cross-functional teams to deliver high-quality solutions that meet critical schedules.

If you want to accelerate your growth by contributing to real architecture, real RTL, and real silicon not just running regressions this role gives you that runway.

Key Skills and Responsibilities

• Perform full physical design implementation: synthesis,floorplanning, power planning, placement, CTS, routing, extraction, ECOs, and signoff.
• Run and own STA directly: MCMM analysis, derates, OCV/AOCV/POCV, constraint development, and timing closure.
• Executetoplevelintegration: build block abstracts, define timing budgets, runtoplevelSTA, and closechipleveltiming yourself.
• Drive PPA optimizationhandson:identifycritical paths, perform placement/clocking optimizations, and propose RTL fixes.
• Perform IR/EM analysis: run static/dynamic IR drop, EM checks, and implement mitigation strategies.
• Run physical verification: DRC, LVS, ERC, antenna, density, and foundry signoff.
• ExecutelatestageECOs: functional, timing, and physical ECOs across the final closure window.
• Develop automation: writeTcl/Python scripts to improve timing analysis, PPA reporting, and signoff flows.
• Collaborate tightly with RTL, architecture, and verificationto drivetimingawaredesign decisions.
• Participate in design reviewsandmaintainhighqualitydocumentation and design collateral.
• Grow into owning full blocksas you gain confidence and experience.

Job Roles and Responsibilities

• 510years of physical design and STA experience with510successfultapeouts
• Location:Kolkata, India
• Qualifications:B.Tech,M.Tech, Ph. D., in Electrical Engineering, Computer Engineering, or related field
• Deep,handsonexpertisewith:(1) STA:PrimeTimeor Tempus; (2) P&R:Innovus, ICC2, or Fusion Compiler; (3) Synthesis: Genus or Design Compiler; (4) Physical verification:Calibreor Pegasus
• Proven ability to personally close timing on complex,highfrequencydesigns
• Strong understanding of:Clocking (mesh,Htree,multisourceCTS), Power grid design, IR/EM analysis,Advancednodephysical effects (variation, SI, RC extraction)
• Strong scripting skills (Tcl, Python, Shell)
• Experience with AI/ML accelerators, GPUs, DSPs, orhighperformancecompute is a plus.
• Ability to work in afastmoving,highownershipstartup environment.
• Experience in collaborating with engineering teams
• Strong analytical and problem-solving skills
• Excellent communication and teamwork skills

Why This Role Matters

• You are the engineer who ensures the chip meets frequency, power, and area targets.
• You directly drive timing closure, IR/EM integrity, and signoff quality.
• Yourhandsonexecutiondetermineswhether the chip tapes out on schedule.

Why Join Us

• Architect and execute the backend flow for agroundupAI accelerator.
• Owntoplevelphysical design and STA with real autonomy.
• Work with a small, elite team where your contributions directly shape the silicon.
• High impact, high ownership, andearlystageequity.