Physical Design Engineer

Role Overview

The Implementation (RTL to GDSII) Engineer is responsible for the complete physical design execution of ASIC and SoC designs, starting from RTL handoff to final GDSII tape-out. The role includes floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, physical verification, and signoff across advanced technology nodes. The engineer works closely with RTL, Design Verification, DFT, STA, and signoff teams to meet Power, Performance, Area, Thermal, Schedule (PPATS) targets.

Core Responsibilities (All Levels)

• Execute end-to-end RTL to GDSII physical design flow for block, subsystem, and full-chip designs
• Perform floorplanning, power planning, placement, CTS, and routing
• Drive multi-corner multi-mode (MCMM) static timing analysis and closure
• Ensure physical verification signoff (DRC, LVS, ERC)
• Analyze and close IR drop, EM, and signal integrity issues
• Optimize Power, Performance, Area, Thermal and Schedule (PPATS)
• Support low-power implementation using UPF/CPF methodologies
• Collaborate with RTL, DV, DFT, STA, and signoff teams
• Develop automation and improve RTL-to-GDSII methodologies

Senior Implementation Engineer 3 to 5 Years

• Handle block-level physical design under guidance
• Perform initial floorplanning, placement, CTS, and routing
• Run STA checks and identify setup and hold violations
• Support timing ECOs and congestion fixes
• Perform basic physical verification (DRC, LVS)

Lead Implementation Engineer 6 to 9 Years

• Own block or subsystem-level RTL-to-GDSII implementation and closure
• Drive power planning, CTS strategy, and advanced timing closure
• Perform detailed MCMM timing analysis across all corners and modes
• Resolve congestion, IR drop, and noise issues
• Integrate DFT and low-power requirements into physical design
• Support full-chip integration and tape-out readiness

Member Technical Staff / Principal Implementation Engineer 10+ Years

• Define RTL-to-GDSII implementation strategy and signoff methodology for SoCs
• Own full-chip physical design signoff and tape-out execution
• Drive PPA optimization on advanced nodes (7nm, 5nm, 3nm)
• Lead late-stage timing, IR/EM, and noise issue resolution
• Develop and standardize best practices, checklists, and automation frameworks
• Mentor implementation engineers and provide technical leadership
• Interface with customers, foundries, and EDA vendors

Tools & Skills

• Physical Design Tools: Synopsys Design Compiler, Fusion Compiler, ICC2
• Cadence Tools: Genus, Innovus, Tempus
• Timing Analysis: Synopsys PrimeTime
• Physical Verification: Siemens Calibre (DRC, LVS, ERC)
• Power & Reliability: IR drop, EM, noise analysis
• Scripting: Tcl (mandatory), Perl, Python, Shell