Physical Design Engineer

Job Description

M.E./M.Tech in Electronics/Electrical Engineering with 6 Years of strong, hands-on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Should have experience in 28nm & below technologies (preferably 20nm & below).

Requirement

• 6+ years of ASIC/SoC Physical Design experience with multiple tapeouts.
• Strong hands-on expertise in Cadence Innovus: floorplan, place/opt, CTS, route, and ECO closure.
• Proven ownership of Top-level (TOP) integration and Hierarchical flow (HFLOW) for large designs.
• Solid timing closure skills (setup/hold), MMMC, constraints/exceptions, and QoR optimization.
• Experience across advanced and lower/mature nodes (e.g., 3/4/5/7nm).
• Strong understanding of physical design signoff readiness: congestion/routability, SI-aware optimization, and coordination for DRC/LVS/ESD, IR/EM.
• Mandatory scripting/automation: strong Tcl (Innovus), plus Python/Perl/Shell preferred.
• Ability to lead closure discussions across STA/DFT/Synthesis/CAD and mentor engineers to meet tapeout schedules.