PDK Verification Engineer

PDK

Experience : 4 years

Location : Bangalore

Title: CDS QA Engineer Role and Responsibilities: The PCELL QA Engineer is responsible for ensuring the Quality Analysis of parameterized cells (PCells) used in Samsung PDKs. The role involves regression testing of PCell, running DRC, LVS on pcells, callback, cdf, techfile across multiple metal stacks and process nodes. The engineer will work closely with PCell developers and the QA Team to drive issue resolution and continuous improvement. Execute CDS unitQA - PCell, lvs on pcells, drc on pcells, netlisting, simulation, callback, cdf, techfile across process nodes Develop/Maintain Regression test suites and execute them to validate PDK wrt pcells, techfiles Skill Requirements: Tools: Cadence Virtuoso (Maestro, ADE-XL), Compiler, Calibre DRC, LVS, HSPICE, Spectre PDK Validation: PCell testing, netlisting, simulation, extraction, schematic/layout creation Technologies: FINFET & CMOS, 5nm/7nm/14nm nodes Scripting: Cadence SKILL for QA Automation, S hell/unix scripting, Python QA Flows & Versioning: Git, Jenkins, regression flows, issue triaging with PDK/dev teams, QA matrix tracking, JIRA, confluence Good to have: Experience: 4 Years Qualifications: B.Tech/B.E/M.Tech/M.E

Interested,please share your updated resume to janagaradha.n@acldigital.com