Memory Layout Engineer

Job Title: Memory Layout Engineer

Location: Bangalore

Experience: 38 Years

Job Description:

We are seeking a highly skilled Memory Layout Engineer to join our VLSI design team in Bangalore. The ideal candidate will have strong hands-on experience in advanced technology nodes and a solid foundation in physical layout concepts, with mandatory exposure to Samsung Foundry processes.

Key Responsibilities:

• Perform memory layout design for advanced semiconductor nodes including 2nm, 3nm, and 4nm (lower node experience is highly preferred).
• Develop high-quality, DRC/LVS-clean layouts adhering to foundry and design guidelines.
• Work closely with circuit design, verification, and physical design teams to ensure layout meets performance, power, and area targets.
• Optimize layouts for density, yield, and manufacturability.
• Resolve complex layout-related issues across the design cycle.

Required Skills & Qualifications:

• 38 years of hands-on experience in memory layout design.
• Strong understanding of fundamental and advanced layout concepts.
• Proven experience working on advanced technology nodes (2nm/3nm/4nm).
• Mandatory experience with Samsung Foundry processes and design rules.
• Proficiency with industry-standard layout tools.
• Strong debugging, analytical, and problem-solving skills.

Preferred Qualifications:

• Experience with lower technology nodes is an added advantage.
• Good understanding of physical verification and sign-off flows.