Lead RTL Engineer

Were hiring: Lead RTL Engineer

Location: Bangalore (5 days WFO)

Experience: 7+ years

We are hiring for a deep-tech semiconductor company building a high-performance signal-processing ASIC - a multi-core vector processor with a custom ISA for deterministic, time-critical workloads across defense, 5G, and test & measurement markets.

We are looking for a hands-on Lead RTL Engineer who can translate architecture specifications into clean, synthesizable SystemVerilog RTL, while leading a small RTL team through the full design cycle.

What youll own

• Translate architecture specs into synthesizable SystemVerilog RTL
• Lead and review RTL work for a team of 5-7 RTL engineers
• Own RTL coding standards, linting rules, and design methodology
• Drive synthesis flow using Design Compiler or Genus
• Define and maintain SDC timing constraints
• Support timing closure using PrimeTime or Tempus
• Coordinate with verification and physical design partners for netlist/GDSII handoff
• Review RTL for correctness, synthesizability, FSM issues, timing hazards, and code quality

Must-have skills

• 7+ years of RTL design experience
• Strong hands-on experience in SystemVerilog
• At least 1 ASIC tapeout through GDSII
• Experience with synthesis, STA, timing closure, and SDC constraints
• Exposure to processor, DSP, vector, or datapath-heavy designs
• Familiarity with 28nm or below process nodes
• Ability to lead a small team while remaining hands-on

Good to have

• VLIW or vector processor design experience
• Deterministic / real-time architecture exposure
• Formal verification awareness / SVA
• FPGA prototyping experience with Vivado