Lead FPGA Design

10+ years experience in Intel/Altera FPGAs (Agilex, Stratix10, Arria10) Architecting FPGA systems with PCIe Gen4/Gen5 Hard IP Expertise in Quartus Prime Pro, Platform Designer, timing closure, transceiver configuration Experience with NVMe/PCIe protocols, DMA engines, and highspeed digital design Ownership of system architecture, FPGA design reviews, floorplanning, and integration Guide team on RTL quality, CDC, SDC constraints, SignalTap debug, and performance optimization

Note:-Altera FPGA and PCIe Gen 3/4/5 experience is mandatory.