Lead Emulation Engineer

Role Overview

We are seeking a highly experienced Lead Engineer FPGA Prototyping to lead the architecture, development, and deployment of scalable FPGA-based prototyping platforms for complex SoCs. This role is pivotal in accelerating pre-silicon software development, system validation, and customer POCs, while enabling seamless alignment with emulation and silicon bring-up.

The candidate will act as a technical leader, driving FPGA prototyping strategy, execution excellence, and cross-functional collaboration across RTL design, verification, software, and system teams.

Key Responsibilities

1. FPGA Prototyping Architecture & Strategy

• Define and drive FPGA prototyping strategy for multi-million gate SoCs and chiplet-based systems
• Architect multi-FPGA partitioning, clock/reset strategies, and high-speed interconnects
• Evaluate and deploy industry platforms (e.g., Synopsys HAPS, Cadence Protium, AMD/Xilinx, Intel FPGA platforms)
• Establish scalable prototyping methodologies aligned with emulation and hybrid verification

2. RTL Integration & Bring-up

• Lead RTL adaptation for FPGA (timing closure, CDC handling, memory modelling, black-boxing)
• Drive synthesis, place & route, and timing closure for large FPGA designs
• Debug complex issues across RTL, FPGA, and board/system level
• Enable early bring-up for SW, FW, and OS teams

3. Performance Optimization & Debug

• Optimize FPGA prototypes for performance, visibility, and stability
• Implement debug strategies using logic analyzers, trace capture, assertions, and instrumentation
• Balance trade-offs between frequency vs. observability

4. Pre-Silicon Software Enablement

• Enable Linux/Android/RTOS boot on FPGA platforms
• Collaborate with software teams to accelerate driver development and system validation
• Support customer demos and POCs using FPGA systems

5. Cross-Platform Convergence

• Align FPGA prototyping with:
• Emulation platforms
• Virtual platforms (SystemC/TLM) like Virtualizer, PA etc
• Silicon bring-up flows
• Drive hybrid prototyping (Emulation + FPGA) use cases

6. Leadership & Mentorship

• Provide technical leadership to FPGA and prototyping teams
• Mentor engineers in partitioning, timing closure, and debug methodologies
• Influence roadmap decisions and vendor engagements

Required Qualifications

• Bachelors/Masters in Electronics, VLSI, Computer Engineering, or related field
• 812+ years of experience in FPGA prototyping / emulation / SoC validation
• Strong expertise in:
• FPGA architectures (AMD/Xilinx, Intel/Altera)
• Multi-FPGA partitioning and interconnect design
• RTL design (Verilog/SystemVerilog)
• Synthesis and P&R tools (Synplify, Vivado, Quartus, etc.)
• Experience with large SoC bring-up on FPGA platforms
• Strong debugging skills across HW/SW boundary

Preferred Qualifications

• Experience with:
• Synopsys HAPS / ZeBu
• Cadence Protium / Palladium
• Know how of SV/UVM based Verification
• Knowledge of high-speed interfaces (PCIe, DDR, Ethernet, UCIe)
• Exposure to chiplet-based architectures and interconnects
• Familiarity with embedded software stacks (Linux, U-Boot, drivers)
• Experience in automating FPGA flows (Python, Tcl, CI/CD pipelines)

Key Competencies

• System-level thinking and architectural depth
• Strong execution and problem-solving mindset
• Ability to work across design, verification, and software domains
• Stakeholder management and communication skills
• Ownership and accountability in high-pressure project environments