IO/Analog Block Layout Engineer

Job Title: Analog/ IO Block Layout Engineer

Location: Bangalore, India

Job Summary

We are seeking a highly skilled IO Layout Engineer with strong experience in advanced process nodes to join our VLSI design team. The ideal candidate will have hands-on expertise in IO and analog block layout, working closely with circuit design, packaging, and foundry teams to deliver high-quality silicon across cutting-edge technologies.

Key Responsibilities

• Design and develop IO and Analog block layouts, including GPIO and DDR interfaces, for advanced technology nodes
• Perform full-chip and block-level IO layout, ensuring compliance with foundry and design rules
• Work on advanced process technologies including TSMC 2nm, 3nm, 5nm and Samsung Foundry 2nm, 4nm (SF)
• Collaborate with circuit designers to optimize layout for performance, power, reliability, and manufacturability
• Execute and resolve DRC, LVS, ERC, EM/IR, and reliability checks
• Review layout against ESD, latch-up, and IO ring requirements
• Interface with foundries to resolve process-related layout issues and implement best practices
• Contribute to layout methodology improvements and automation where applicable

Required Skills & Qualifications

• Strong experience in IO and Analog Layout, including GPIO and DDR
• Proven hands-on experience with advanced nodes:
• TSMC: 2nm, 3nm, 5nm
• Samsung Foundry: 2nm, 4nm
• Solid understanding of advanced DRC/LVS rules and complex design constraints
• Familiarity with ESD, latch-up prevention, EM/IR, and reliability requirements for IO designs
• Proficiency with industry-standard EDA tools (Cadence Virtuoso or equivalent)
• Strong understanding of semiconductor manufacturing processes and layout fundamentals

Experience Level

• Typically 4+ years of relevant experience in IO/Analog layout (flexible based on skill depth)