IC Package Design Engineer

Walk-In Drive: IC Package Design Engineer (3+ Years)

Weekend Hiring Drive HCLTech | Bangalore (Jigani Campus)

HCLTech is hiring skilled professionals for the role of IC Package Design Engineer. If you have a passion for advanced package and PCB design, we invite you to attend our walk-in drive!

Interview Details

• Date: 16 May 2026 (Saturday)
• Time: 9:00 AM 2:00 PM
• Venue: Tower 4, GF caf 3 , HCLTech, Jigani Campus, Bangalore
• Mode: Face-to-Face (F2F)
• SPOC: Mareeswari C M

Role: IC Package Design Engineer

Experience: 3+ Years

Key Responsibilities & Required Skills

• Strong experience in IC Package / Substrate Design (mandatory)
• Hands-on experience with Cadence APD (Allegro Package Designer)
• Good understanding of package/substrate design and assembly rules, especially for flip chip designs
• Exposure to various package technologies such as MCM, Flip-Chip, Wire Bond, 2.5D, 3D (added advantage)
• Expertise in high-speed complex package & PCB design, including:
• HDI
• Blind & Buried Via technologies
• Hands-on experience in PCB designs involving high-speed interfaces, such as:
• DDR / GDDR
• PCIe / SERDES / HSIO
• Strong exposure to:
• Stack-up design
• DFM (Design for Manufacturability) and DFA (Design for Assembly) rules
• Constraint setting in layout tools

Technical / Soft Skills

• Hands-on experience with Cadence Allegro PCB Layout Design (including constraint setup)
• Expertise in IC Package / Substrate Design workflows
• Experience with CAM verification tools
• Ability to work independently with customer SPOCs
• Experience across end-to-end design phases (Net-in to Gerber generation)

How to Apply

Candidates who are unable to attend the walk-in can share their profiles via email:

mareeswari.cm@hcltech.com

Please include the following details:

• Name
• Total Experience
• Current CTC
• Expected CTC
• Notice Period
• Counter Offer (if any)

Thanks

Mareeswari C M