Job Description

Key Responsibilities:

Develop and implement comprehensive verification plans for HBM4/4e IP and Subsystem.
Create and maintain testbenches, test cases, and verification environments using System verilog and UVM methodology.
Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis.
Collaborate with design engineers to understand design specifications and requirements for IP and subsystems.
Identify and resolve design and verification issues, ensuring high-quality and robust designs.
Generate and analyze verification metrics to track progress and ensure coverage goals are met.
Participate in design and verification reviews, providing technical expertise and insights.
Stay updated with the latest verification technologies and methodologies and apply them to improve verification efficiency and effectiveness.
Mentor junior verification engineers and provide technical guidance.

Requirement

Qualifications

Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field.
10+ years of experience in design verification, with a focus on HBM/DDR (DDR5/DDR4/DDR3) IP or Subsystem verification.
Knowledge of other memory protocols is a plus.
Proficiency in verification languages and methodologies, such as System Verilog, UVM, and other industry-standard tools.
Strong understanding of digital design concepts, RTL coding, and simulation.
Experience with scripting languages (e.g., Python, Perl, Tcl) for automation and tool integration.
Excellent problem-solving skills and attention to detail.
Strong communication and teamwork skills, with the ability to work effectively in a collaborative environment.
Proven track record of successfully verifying complex IP blocks and subsystems.

HBM/DDR Subsystem Verification- Lead