FPGA design engineer

Key Responsibilities:

• Design efficient RTL implementations targeting FPGAs
• Translate MATLAB/Simulink models into RTL
• Develop RTL architecture & microarchitecture based on algorithm requirements
• Implement RTL using VHDL / Verilog / SystemVerilog
• Work on blocks like ORAN, Digital Filters, FFT engines, Time Sync protocols, JESD 2.5
• Perform functional verification, linting & synthesis
• FPGA implementation, performance validation & board bring-up
• Collaborate with verification & firmware teams for end-to-end integration

Required Skills:

• Strong VHDL & RTL design expertise
• Strong fundamentals in Digital Signal Processing
• Experience in FPGA design flow synthesis, STA, timing closure
• Hands-on with AMD (Xilinx) / Altera tool flows
• Experience with Agilex FPGA or Zynq RFSoC preferred
• Debugging RTL & simulation mismatches

Preferred Domain Experience:

• ORAN / Wireless (L2/L3 switching, control & data planes)
• OR
• Wireline Ethernet packet processing (Routing/Switching complexity)
• OR
• Radar signal processing (Channel coding, modulation/demodulation)