Formal Verification Engineer

Formal Verification Engineer

Location: Bangalore, Hyderabad, Noida

Experience:

310 Years

Job Description:

We are looking for a skilled Formal Verification Engineer with strong expertise in formal methods to validate complex digital designs. The candidate will be responsible for ensuring design correctness using advanced formal verification techniques.

Key Responsibilities:

• Develop and execute formal verification strategies for RTL designs.
• Write SystemVerilog Assertions (SVA) and properties.
• Perform property checking, equivalence checking, and model checking.
• Debug and analyze formal failures and counterexamples.
• Collaborate with design and verification teams to close coverage gaps.
• Ensure functional correctness and improve design quality.
• Drive formal coverage closure and ensure completeness.
• Participate in design reviews and provide verification insights.

Required Skills:

• Strong understanding of digital design fundamentals.
• Hands-on experience with:
• SystemVerilog Assertions (SVA)
• Formal verification methodologies
• Experience with formal tools such as:
• Cadence JasperGold
• Synopsys VC Formal
• Siemens Questa Formal
• Knowledge of RTL design (Verilog/SystemVerilog).
• Understanding of protocols (AXI, PCIe, AMBA, etc.).
• Strong debugging and analytical skills.

Preferred Skills:

• Knowledge of CDC/RDC verification concepts.
• Exposure to coverage-driven verification.
• Experience with scripting languages (Python/Shell/Perl).
• Familiarity with simulation-based verification (UVM).