Field-Programmable Gate Arrays Engineer

Were Hiring: FPGA RTL Design Engineers | ORAN Domain | Pre-Silicon Experience

Priority Hiring | Immediate Joiners Preferred

Role: FPGA RTL Design Engineer

Location: Pan India

Experience: 7 15 Years (FTE)

Mandatory: Minimum 5 Years Pre-Silicon Experience

What Youll Work On

• Design and develop high-performance RTL solutions for FPGA platforms
• Convert MATLAB/Simulink algorithms into RTL implementations
• Build components like:
• ORAN modules & IP compression
• Digital Filters & FFT Engines
• Time Synchronization Protocols
• High-speed interfaces (JESD)
• Perform RTL verification, synthesis & timing closure
• FPGA implementation & performance validation
• Collaborate with cross-functional teams for end-to-end product delivery

Must-Have Skills

Strong RTL design expertise in VHDL / Verilog / SystemVerilog

Solid understanding of Digital Signal Processing (DSP)

Hands-on with FPGA design flow (Synthesis, STA, Timing Closure)

Experience with:

• AMD (Xilinx Zynq RFSoC)
• Intel (Altera Agilex FPGA)
• Debugging RTL & simulation mismatches
• Exposure to UVM/SystemVerilog (good to have)

Preferred Experience

Telecom / ORAN Domain (Highly Preferred)

• Control & Data Plane understanding
• Wireless protocol stack (L2/L3)
• Packet processing

Alternate Domain Experience

• Wireline Ethernet (Routing/Switching)
• Radar Signal Processing (Modulation/Demodulation, Coding)

Qualifications

B.Tech / M.Tech Electronics / Electrical or related

Experience with tools: ModelSim, Questa, Vivado, Quartus

Scripting knowledge (Python / Tcl / Perl) is a plus

Interested or know someone who fits?

Send your resume to sreekanth.g@rapinnotech.com