Field-Programmable Gate Arrays Engineer
ACL Digital
3 - 6 years
Hyderabad
Posted: 21/04/2026
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Job Description
FPGA Design Engineers
Experience : 3-6 years
Location : Hyderabad
Looking for hands-on experience in Xilinx Vivado, RTL to bitstream flow, and strong digital design fundamentals (timing, CDC, AXI, SPI, I2C, UART).
Candidates with FPGA bring-up, debugging (ILA/Chipscope), and scripting (TCL/Python) skills are highly preferred.
Location: Hyderabad | Notice Period: 030 Days
Apply now: janagaradha.n@acldigital.com
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