Field-Programmable Gate Arrays Engineer

RTL - FPGA Design Engineer

Experience : 5+years

Location : Hyderabad

Silicon Design Engineer (RTL Design & Development) Hyderabad

Looking for experienced professionals skilled in FPGA design using VHDL/Verilog and Xilinx tools.

Hands-on expertise in protocols like Ethernet, PCIe, SPI, I2C, USB, DDR/SDRAM, and DMA is essential.

Strong debugging skills at device and board level, plus experience with lab test equipment required.

Proficiency in scripting (Python/Perl/TCL) and solid documentation abilities are expected.

Experience: 5+ years | Notice Period: 030 days | Contact: janagaradha.n@acldigital.com