Field-Programmable Gate Arrays Engineer

Silicon Design Engineer (RTL Design & Development)

Location : Hyderabad

Experience : 5+ years

Looking for professionals with 5+ years of experience in RTL design, VHDL/Verilog, and FPGA development using Xilinx tools.

Strong knowledge of high-speed interfaces (PCIe, Ethernet, USB, SPI, I2C) and memory architectures (DDR/SDRAM/DMA) is essential.

Hands-on debugging experience at device and board level using logic analyzers, traffic generators, and test tools is required.

Exposure to scripting (Python/Perl/TCL) and ability to create technical documentation is a plus.

Location: Hyderabad | Notice Period: 030 Days

Apply now: janagaradha.n@acldigital.com