Field-Programmable Gate Arrays Engineer
ACL Digital
2 - 5 years
Hyderabad
Posted: 25/04/2026
Job Description
RTL - FPGA Design Engineer
Experience : 5+years
Location : Hyderabad
Silicon Design Engineer (RTL Design & Development) Hyderabad
Looking for experienced professionals skilled in FPGA design using VHDL/Verilog and Xilinx tools.
Hands-on expertise in protocols like Ethernet, PCIe, SPI, I2C, USB, DDR/SDRAM, and DMA is essential.
Strong debugging skills at device and board level, plus experience with lab test equipment required.
Proficiency in scripting (Python/Perl/TCL) and solid documentation abilities are expected.
Experience: 5+ years | Notice Period: 030 days | Contact: janagaradha.n@acldigital.com
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