Experience

5+ years of handson experience in DesignforTest (DFT) for ASIC / SoC designs.

Scope of Work

Implement and support DFT architectures for digital / mixedsignal SoCs, including:

Scan (full/partial), scan compression

MBIST / LBIST

JTAG/IJTAG / boundary scan

Execute DFT RTL insertion, integration, and verification in collaboration with RTL, PD, and DV teams.

Review and influence clocking, reset, and lowpower intent from a DFT perspective.

Run DFT tool flows and support DFT signoff (coverage, rule checks, readiness for ATPG).

Debug DFT issues across RTL, synthesis, and gatelevel netlists.

Support test engineering handoff, pattern readiness, and postsilicon debug as needed.

Maintain DFT specs, checklists, and documentation; capture lessons learned.

Required Skills

Strong fundamentals in digital design (clocks, resets, timing, FSMs).

Solid experience with:

Scan insertion and coverage analysis

MBIST/LBIST architectures

Test modes and DFT verification

Handson with industry DFT tools (one or more):

Siemens Tessent, Synopsys DFT Compiler, or equivalent

Proficiency in Verilog / SystemVerilog.

Ability to work independently on assigned DFT blocks or subsystems.

GoodtoHave

Experience with mixedsignal / PMIC / memoryinterface SoCs.

Exposure to postsilicon debug or yieldrelated DFT issues.

Tcl / Python scripting for flow automation.

Prior experience working as vendor/EWF in large semiconductor programs.

DFT Engineer