Design Verification Engineer VLSI

JD:

Experience: 6+ Years, No Freshers Profile will be accepted.

Proven working experience within the semiconductor industry in constraint random functional and formal verification

Expertise in hardware verification using SystemVerilog/UVM and Specman E. Experience with communication protocols (inc. Ethernet, CAN/CANXL, SPI). Also experience with AMBA protocols and Infineon internal protocols (e.g., FPI, SRI)

Experience with the following Infineon IPs: XSPI, CANXL, MCMCAN, DRE, LETH, XGETH.

Knowledge of using regression and coverage analysis tools as well as knowledge of test bench qualification

Knowledge and experience with functional safety according to ISO26262

Working experience in international and cross-functional technical teams within a multi-cultural environment

Excellent English communication skills

Tasks

Develop SystemVerilog compliant verification environments

Creation of verification plans and execution of coverage closure

Provide relevant reports to show progress

Run regressions / help set up automatic regressions

Skillset

Proven working experience within the semiconductor industry in constraint random functional and formal verification

Expertise in hardware verification using SystemVerilog/UVM and Specman E. Experience with communication protocols (inc. Ethernet, CAN/CANXL, SPI). Also experience with AMBA protocols and Infineon internal protocols (e.g., FPI, SRI)

Experience with the following Infineon IPs: XSPI, CANXL, MCMCAN, DRE, LETH, XGETH.

Knowledge of using regression and coverage analysis tools as well as knowledge of test bench qualification

Knowledge and experience with functional safety according to ISO26262

Working experience in international and cross-functional technical teams within a multi-cultural environment

Excellent English communication skills

Services

Testcases ready for regression

Qualified verification environment using SystemVerilog and SpecMan e

Verification sign-off report fulfilling defined KPIs (e.g. 100% coverage)

Intermediate progress / KPI status reports on agreed frequency

Debug support to reach sign-off quality targets of IPs

Automation for regression runs (Jenkins)

Tools

Xcelium, Vmanager Enterprise edition, System Verilog, VHDL, knowledge of scripting languages perl / python, automation scripts with Jenkins