Design Verification Engineer

Were Hiring: Senior Design Verification Engineer (5+ Years)

Location: Bangalore

Notice Period: Immediate to 30 Days

We are looking for an experienced Senior Design Verification Engineer to join our dynamic team.

Key Requirements:

• 5+ years of experience in Design Verification
• Strong hands-on experience in SoC Verification
• Expertise in PCIe and UCIe protocols
• Good exposure to GLS (Gate Level Simulation)
• Strong knowledge of System Verilog / UVM
• Experience in debugging, testbench development, and coverage closure
• Understanding of SoC architecture, interconnects, and high-speed protocols

Preferred Skills:

• Experience with verification methodologies and tools
• Strong problem-solving and debugging skills
• Ability to work in a fast-paced environment

Interested candidates can share their resumes to:

Sethupathi.V@univisiontechnocon.com

Hashtags:

#Hiring #DesignVerification #SoC #PCIe #UCIe #GLS #SystemVerilog #UVM #SemiconductorJobs #BangaloreJobs #ImmediateJoiners #VerificationEngineer #TechHiring #VLSIJobs