Design Verification Engineer
Talent Destination
2 - 5 years
Chennai
Posted: 04/04/2026
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Job Description
Key Responsibilities
- Verify Ethernet / USB IPs using SystemVerilog & UVM
- Develop testbench, testcases, sequences, and scoreboards
- Work on protocol validation (Ethernet: 1G100G, USB: 2.0/3.x/Type-C)
- Debug RTL issues and analyze waveforms
- Perform coverage closure (functional + code + assertions)
- Run regressions and ensure protocol compliance
Required Skills
- Strong SystemVerilog & UVM
- Experience in Ethernet (MAC/PHY) and/or USB protocols
- Knowledge of SVA, coverage-driven verification
- Familiar with tools: VCS / Xcelium / Questa, Verdi/DVE
- Basic scripting (Python/Perl/Shell)
Good to Have
- Experience with VIPs (Synopsys/Cadence/Mentor)
- Knowledge of USB Type-C / USB-PD / IEEE 802.3
- AMBA (AXI/AHB) exposure
Education
- B.E / B.Tech / M.Tech (ECE/EEE/CSE)
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