Design Verification Engineer – Ethernet

About the Role

We are seeking a skilled and motivated Design Verification (DV) Engineer with strong hands-on Ethernet verification experience to join our Datacenter Division. The ideal candidate will bring a solid foundation in SystemVerilog/UVM-based verification, a history of contributing to multiple successful tapeouts, and specific expertise in Ethernet protocol verification and UALink. This role offers the opportunity to work on cutting-edge datacenter networking silicon and directly contribute to next-generation Ethernet and accelerator interconnect IP development.

Key Responsibilities

• Execute and contribute to the Design Verification effort for Ethernet IP blocks and accelerator interconnect interfaces targeted at high-performance datacenter applications
• Develop and maintain UVM-based testbench environments, including test cases, scoreboards, monitors, and functional coverage models
• Implement and verify protocol features with a focus on UAL and UEC functionality
• Write and review testplans in collaboration with design and architecture teams, ensuring comprehensive coverage of protocol features and corner cases
• Develop and integrate BFMs (Bus Functional Models) and protocol checkers for Ethernet and UALink interface verification
• Debug complex simulation failures and work with design engineers to drive issues to root cause and resolution
• Contribute to coverage closure analyze functional and code coverage results and develop targeted tests to close coverage holes
• Support formal verification efforts where applicable, including the development of assertions and properties for protocol compliance
• Participate actively in tapeout closure activities, including regression management, sign-off reviews, and final verification milestones
• Collaborate across teams work closely with design, architecture, and validation engineers to ensure seamless handoff and high silicon quality

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronic Engineering, Computer Science, or a related field
• 4+ years of hands-on Design Verification experience, with a strong focus on Ethernet or high-speed networking/interconnect IP
• Demonstrated experience across multiple tapeout cycles, with active participation in verification closure and sign-off
• Strong proficiency in SystemVerilog and UVM-based verification methodology
• Hands-on experience with UALink and/or UEC verification, including feature-level test development and protocol compliance checking
• Solid understanding of Ethernet protocol fundamentals framing, flow control, MAC/PCS layer behavior, and error handling
• Experience with functional coverage modeling and assertion-based verification (ABV)
• Strong debug and analytical skills, with the ability to trace failures across complex multi-block environments
• Good communication and collaboration skills, with experience working in cross-functional teams

Preferred Qualifications

• Prior exposure to datacenter, HPC, AI/ML accelerator, or cloud networking silicon development
• Familiarity with 400G/800G Ethernet standards and datacenter networking architectures
• Familiarity with UALink consortium specifications and the broader AI/ML accelerator interconnect ecosystem
• Knowledge of CBFC and LLR mechanisms and their verification implications
• Experience with emulation platforms (e.g., Palladium, Zebu) for accelerated verification
• Familiarity with formal verification tools (e.g., JasperGold, VC Formal)
• Experience with Python or Perl for testbench automation and scripting