Design for Test (DFT) Engineer

Hiring: Design for Test (DFT) Engineer | 715 Years | Bangalore / Hyderabad

We are actively looking for experienced DFT Engineers with strong expertise in scan, ATPG, MBIST, and DFT verification for complex SoC/ASIC designs. If you have end-to-end DFT implementation experience from RTL to silicon bring-up, this is a great opportunity to work on cutting-edge semiconductor projects.

Role Summary

You will be responsible for defining and implementing DFT architecture, ensuring high fault coverage, and supporting silicon bring-up for advanced chip designs.

Mandatory Technical Skills (Strict Screening Criteria)

Hands-on experience in Scan Insertion & ATPG

Experience with at least one tool suite:

Synopsys (DFT Compiler / TetraMAX / TestMAX)

Cadence Modus

Mentor Tessent (Scan / MBIST / EDT)

Strong understanding of:

Scan Architecture (Full Scan / Compression)

Stuck-at & Transition Fault Models

MBIST / LBIST concepts

JTAG / IEEE 1149.1

Experience in:

Debugging DRC & coverage issues

Verilog / SystemVerilog

Gate-Level Simulation (GLS) for test modes

Good to Have

Hierarchical DFT flows

Low-power DFT implementation

Scan chain reordering & physical awareness

Silicon bring-up / ATE debug exposure

Automation using Tcl / Perl / Python

Key Responsibilities

Define and implement DFT architecture (block/full chip)

Perform scan insertion & DFT rule checks

Generate & debug ATPG patterns

Achieve target fault coverage

Collaborate with Physical Design for timing closure

Support silicon bring-up & tester correlation

Drive coverage closure and yield improvement

Experience Expectations

712 Years: Lead subsystem/full-chip DFT, architecture contribution, mentoring

1315 Years: Own full-chip DFT sign-off, drive methodology & cross-functional leadership

Location & Work Setup

Bangalore / Hyderabad

Full-Time Role

Notice Period Preference

Immediate joiners

Candidates serving up to notice period

Compensation & Benefits

Budget: Experience 5 (Best in industry)

Leaves: 14 annual + 6 sick leaves

Insurance: Available (details to be shared)

Notice Buyout: Case-to-case basis

Important Screening Guidelines

Must clearly mention:

Tools expertise (with hands-on clarity)

Role (Block / Subsystem / Full chip)

Fault coverage achieved (%)

Node / Chip size / SoC details

Current & Expected CTC

Notice period & location

Avoid profiles with:

Only academic DFT exposure

Validation/ATE-only background

RTL-only experience without DFT ownership

Interested or know someone perfect for this role?

Lets connect!

naresha.r@nityo.com

WhatsApp: 8746012727

Feel free to share this opportunity with your network!

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